1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a ramp voltage generator, an image sensing device including the same and method for driving the image sensing device.
2. Description of the Related Art
Image sensing devices capture images using photosensitive properties of semiconductors. Image sensing devices are often classified into charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. CMOS image sensors allow for both analog and digital control circuits to be directly realized on a single integrated circuit (IC), making CMOS image sensors the most widely used type of image sensor.
Electronic devices, such mobile phones may be fabricated with built-in image sensing devices. The image sensing devices need to perform high speed operations to improve the overall performance of the mobile apparatus. This has resulted in many specialized technologies being developed for image sensing devices. Particularly, technologies for reducing analog-to-digital converter (hereinafter, referred to as “ADC”) readout times of image sensing devices have being recently proposed. For example, a 2-step ADC developed from a single-slope ADC has been proposed. The single-slope ADC requires a clock with a cycle of “210=1024” in order to output a digital signal of 10 bits, whereas the 2-step ADC requires a clock with a cycle of “23+27=136” by outputting 3 bits of the digital signal using a coarse clock and outputting the other 7 bits of the digital signal using a fine clock. Ideally, the readout time could be reduced by a ratio of “136/1024”. Since the coarse clock has a frequency lower than that of the fine clock in order to ensure the settling time of the coarse clock, the readout time is longer than the ideal readout time. However, the readout time of the 2-step ADC may be effectively reduced compared with the readout time of the single-slope ADC. In addition, since the 2-step ADC may be realized in a small circuit area, it is generally preferred as a technology that can be applied to image sensing devices having a high number of pixels and operating at high speed.
The 2-step ADC uses a coarse ramp voltage corresponding to the coarse clock and a fine ramp voltage corresponding to the fine clock. For example, the 2-step ADC may output a digital signal of 3 bits corresponding to a voltage level of a pixel signal (i.e., an analog signal) based on the coarse ramp voltage having a predetermined slope, and then may output a digital signal of 7 bits corresponding to the voltage level of the pixel signal based on the fine ramp voltage having the predetermined slope. Typically, an image sensing device includes a ramp voltage generator for generating the coarse ramp voltage and the fine ramp voltage.
FIG. 1 is a diagram illustrating a conventional ramp voltage generator.
Referring to FIG. 1, the conventional ramp voltage generator includes a source current generation block 11, a coarse ramp voltage generation block 13, and a fine ramp voltage generation block 15.
The source current generation block 11 generates a first source current I1 in response to a first bias voltage VNB and a second bias signal VPB corresponding to the first source current I1.
For example, the source current generation block 11 includes a first sinking section N1 and a first sourcing section P0. The first sinking section N1 is coupled between an output terminal of the second bias voltage VPB and a ground voltage terminal, and sinks the first source current I1 in response to the first bias voltage VNB. For example, the first sinking section N1 includes a NMOS transistor having a gate coupled to an input terminal of the first bias voltage VNB, and a drain and a source coupled between the output terminal of the second bias voltage VPB and the ground voltage terminal. The first sourcing section P0 is coupled between a power supply voltage terminal and the output terminal of the second bias voltage VPB, and sources the source current I1 in response to the second bias voltage VPB. For example, the first sourcing section P0 includes a PMOS transistor having a gate and a drain coupled to the output terminal of the second bias voltage VPB, and a source coupled to the power supply voltage terminal.
The coarse ramp voltage generation block 13 generates a first mirror current I2 varied by a coarse operating unit, for example, corresponding to 128 least significant bits (LSB), in response to the second bias voltage VPB and first to Xth coarse ramp control signals CR_CTRL<1:X>, and generates a coarse ramp voltage VCR based on the first mirror current I2.
For example, the coarse ramp voltage generation block 13 includes first mirroring sections P1 to PX, first switching sections SW1 to SWX, and a first resistor section R_CR. The first mirroring sections P1 to PX are coupled between the power supply voltage terminal and first to Xth mirroring nodes MN1 to MNX, and resource the first mirror current I2 in response to the second bias voltage VPB. For example, the first mirroring sections P1 to PX include first to Xth PMOS transistors respectively having gates coupled to an input terminal of the second bias voltage VPB and sources and drains coupled between the power supply voltage terminal and the first to Xth mirroring nodes MN1 to MNX. The first switching sections SW1 to SWX are coupled between the first to Xth mirroring nodes MN1 to MNX and an output terminal of the coarse ramp voltage VCR, and generate the first mirror current I2 decreased by the coarse operating unit during a coarse conversion period in response to the first to Xth coarse ramp control signals CR_CTRL<1:X>. For example, the first switching sections SW1 to SWX include first to Xth switching elements which are sequentially open during the coarse conversion period in response to the first to Xth coarse ramp control signals CR_CTRL<1:X>. The first resistor section R_CR may be coupled between the output terminal of the coarse ramp voltage VCR and the ground voltage terminal. For example, the first resistor section R_CR includes a resistance element.
The fine ramp voltage generation block 15 generates a second mirror current I3 varied by a fine operating unit, for example, corresponding to 1 LSB, in response to the second bias voltage VPB and first to Zth fine ramp control signals FR_CTRL<1:Z>, and generates a fine ramp voltage VFR based on the second mirror current I3.
For example, the fine ramp voltage generation block 15 includes second mirroring sections PX+1 to PX+Z, second switching sections SW11 to SW1Z, and a second resistor section R_FR. The second mirroring sections PX+1 to PX+Z are coupled between the power supply voltage terminal and first to Zth mirroring nodes MNX+1 to MNX+Z, and resource the second mirror current I3 in response to the second bias voltage VPB. For example, the second mirroring sections PX+1 to PX+Z include first to Zth PMOS transistors respectively having gates coupled to the input terminal of the second bias voltage VPB and sources and drains coupled between the power supply voltage terminal and the first to Zth mirroring nodes MNX+1 to MNX+Z. The second switching sections SW11 to SW1Z are coupled between the first to Zth mirroring nodes MNX+1 to MNX+Z and an output terminal of the fine ramp voltage VFR, and generate the second mirror current I3 increased by the fine operating unit during a fine conversion period in response to the first to Zth fine ramp control signals FR_CTRL<1:Z>. For example, the second switching sections SW11 to SW1Z include first to Zth switching elements which are sequentially closed during fine conversion period in response to the first to Zth fine ramp control signals FR_CTRL<1:Z>. The second resistor section R_FR may be coupled between the output terminal of the fine ramp voltage VFR and the ground voltage terminal. For example, the second resistor section R_FR includes a resistance element.
In the conventional image sensing device, a mismatch may be exist between the coarse ramp voltage generation block 13 and the fine ramp voltage generation block 15. For example, a mismatch in a fabrication process may occur between the first to Xth PMOS transistors included in the first mirroring sections P1 to PX and the first to Zth PMOS transistors included in the second mirroring sections PX+1 to PX+Z, or a mismatch in the fabrication process may occur between load resistors of the coarse ramp voltage generation block 13 and the fine ramp voltage generation block 15.
For this reason, when a mismatch occurs between the coarse ramp voltage generation block 13 and the fine ramp voltage generation block 15, a mismatch between the coarse ramp voltage VCR and the fine ramp voltage VFR may occur. In this case, a circuit using the coarse ramp voltage VCR and the fine ramp voltage VFR, for example, the 2-step ADC, outputs a digital signal corresponding to a missed code (i.e., an erroneous code). FIGS. 2A and 2B are graphs illustrating the relation between the range of an analog signal (i.e., ADC range) and a corresponding digital signal (i.e., count code) to which the 2-step ADC may convert the analog signal. For example, when the slope of the fine ramp voltage VFR is lower than that of the coarse ramp voltage VCR, a linearity error may occur as illustrated in FIG. 2A. When the slope of the fine ramp voltage VFR is higher than that of the coarse ramp voltage VCR, a linearity error may occur as illustrated FIG. 2b.
Therefore, when the linearity error occurs, the 2-step ADC outputs a digital signal corresponding to a missed code in converting an analog signal.